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| NCP5021 High Voltage White LED Driver with Ambient Light Sensing The NCP5021 product is a single output boost LED driver capable of driving up to 8 LEDs in series for portable backlight applications. The built-in DC/DC converter is based on a high efficient PWM boost structure with 32 V output voltage span. It provides a peak 90% efficiency together with a 1% I-LED current tolerance. Features http://onsemi.com 1 * * * * * * * * * 2.7 to 5.5 V Input Voltage Range 90% Peak efficiency with 4.7 mH / 150 mW Inductor Gradual Dimming Built-in (Automatic Fade In/Fade Out Effect) Integrated Ambient Light Sensing Automatically Adjusts the LCD Backlight Contrast Built-in Zero Current Load Leakage under Idle Mode Support the Full I2C Protocol with Address Extension Tight 1% I-LED Tolerance Ultra Thin 0.5 mm QFN16 Package This is a Pb-Free Device UQFN16 MU SUFFIX CASE 523AF MARKING DIAGRAM 5021 ALYWG G 5021 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package Typical Applications * Cellular Phone, Smartphone * Portable Media Player (PMP) * Global Positioning System (GPS) +Vbat C1 4.7mF/6.3V SCL SDA GND SFH5711 U3 Log C3 100nF R3 4 R4 L1 4.7mH 15 Vbat 1 SCL 2 SDA 3 I2CADR 4 VSB U1 NCP5021 Lx Vos 13 1.0 mF/50 V 16 R3 470R C2 NSR0240M2T5G D8 D1 D2 D3 I-Load Max = 25 mA D4 D5 D6 NC NC NC 9 12 11 10 D7 (Note: Microdot may be in either location) PIN CONNECTIONS VOS VCC GND LX SCL SDA I2CADR VSB AMBS IPK IREF GND (Top View) NC = Not Connected NC NC NC FB GND GND 22k GND C4 2.2mH 1 2 220k R1 12k 5 AMBS 7 IREF IPK ORDERING INFORMATION D8 Device NCP5021MUTXG Package UQFN16 (Pb-Free) Shipping 3000 / Tape & Reel R2 6 22k GND GND GND FB 8 14 GND Figure 1. Typical Large Display LED Driver For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2009 May, 2009 - Rev. 0 1 Publication Order Number: NCP5021/D NCP5021 Table 1. PIN DESCRIPTIONS PIN 1 2 3 Name SCL SDA I2CADR Type INPUT, DIGITAL INPUT, DIGITAL INPUT, DIGITAL Description This pin carries the I2C clock to control the DC/DC converter and to set up the output current and the photo sensor. The SCL clock is associated with the SDA signal. This pin carries the data provided by the I2C protocol. The content of the SDA byte is used to program the mode of operation and to set up the output current. This pin is used to select the I2C address of the NCP5021: - I2CADR = Low address = %0111 0010 = $72 - I2CADR = High address = %0111 0100 = $74 In order to avoid any risk during the operation, the digital levels are intended to be hardwired prior to power up the system. This pin provides a switched voltage, derived from the Vbat supply, to bias the external photo sense. The current capability of this voltage is 1 mA. The VSB pin is disconnected when the Shutdown mode has been engaged. This pin senses the voltage developed across the external Photo Bias resistor. Since this is a very high impedance input, cares must be observed to minimize the leakage current and the noise that may influence the photo sense analog function. The bias parameters associated with the AMBS pin are reloaded when the chip resumes from Shutdown to Normal operation. This pin provides the inductor peak current during normal operation. In no case shall the voltage at IPK pin be forced either higher or lower than the 1144 mV provided by the internal reference. This pin provides the reference current, based on the internal band-gap voltage reference, to control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the LED biases. An external current source can be used to bias this pin to dim the light coming out of the LED. In no case shall the voltage at IREF pin be forced either higher or lower than the 1144 mV provided by the internal reference. This pin is the GROUND signal for the analog and digital blocks and must be connected to the system ground. A ground plane is strongly recommended. This pin is the current sense of the series arranged LED. The built-in current mirror will automatically adapt the voltage drop across this pin (typically 400 mV). This pin shall be left open for normal operation. This pin shall be left open for normal operation. This pin shall be left open for normal operation. POWER The external inductor shall be connected between this pin (drain of the internal Power switch) and Vbat. The voltage is internally clamped at 40 V under worst case conditions. The external Schottky diode shall be connected as close as possible to this pin. See Note 1 for ESR recommendations. This pin is the GROUND reference for the DC/DC converter and the output current control. The pin must be connected to the system ground, a ground plane being strongly recommended. Input Battery voltage to supply the analog , the digital blocks and the main Power switch driver. The pin must be decoupled to ground by a 10 mF ceramic capacitor. This pin senses the output voltage supplied by the DC/DC converter. The Vos pin must be bypassed by 1.0 mF/50 V ceramic capacitor located as close as possible to the pin to properly bypass the output voltage to ground. The circuit shall not operate without such bypass capacitor connected to the Vos pin. The output voltage is internally clamped to 40 V maximum in the event of no load situation. NOTE: Due to the very fast dV/dt transient developed during the operation, using a low pass filter is strongly recommended as depicted in the schematic diagram Figure 1. Back side exposed pad is not internally connected and can be either left floating or connected to the system Ground. 4 VSB POWER, OUTPUT INPUT, ANALOG 5 AMBS 6 7 IPK IREF INPUT, ANALOG INPUT, ANALOG 8 9 10 11 12 13 AGND FB NC NC NC Lx POWER INPUT, ANALOG 14 15 16 PGND VBAT Vos POWER INPUT, POWER OUTPUT, POWER NC - Not Connected 1. Using low ESR ceramic capacitor (X5R or better) and low ESR inductor with minimum Eddie losses is mandatory to optimize the DC/DC efficiency. http://onsemi.com 2 NCP5021 Table 2. MAXIMUM RATINGS Symbol VBAT VLX SCL, SDA ESD Power Supply Output Switching Voltage Digital Input Voltage Digital Input Current Human Body Model: R = 1500 W, C = 100 pF (Note 2) Machine Model LLGA16 package Power Dissipation @ TA = +85C (Note 3) Thermal Resistance Junction to Case Thermal Resistance Junction to Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Latch-up current maximum rating per JEDEC standard: JESD78. MSL Moisture Sensitivity Level (Note 4) Rating Value -0.3 < V < 7.0 34 -0.3 < V < VBAT 1 2 200 300 50 130 -40 to +85 -40 to +125 +150 -65 to +150 100 1 Unit V V V mA kV V mW C/W C/W C C C C mA PD RqJC RqJA TA TJ TJmax Tstg Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114 Machine Model (MM) 200 V per JEDEC standard: JESD22-A115 3. The maximum package power dissipation limit must not be exceeded. 4. per IPC/JEDEC standard: J-STD-020A. http://onsemi.com 3 NCP5021 Table 3. POWER SUPPLY SECTION (Typical values are referenced to TA = +25C, Min & Max values are referenced -40C to +85C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted. Symbol Vbat VUVLO VUVLOHY Iout ILKLX VOVP VOVPHYS tstart Rating Power Supply Operating Range Power Supply Undervoltage Lockout Undervoltage Lockout Hysteresis Continuous DC Current in the load, Vout pin @ 3.0 V< Vbat < 5.5 V Power Switch Leakage Current (Lx pin) @ Iout = 0 Output Voltage Overvoltage Protection OVP Output Voltage Hysteresis DC/DC Start time (Cout = 4.7 mF), 3.0 V < Vbat = nominal < 5.5 V from last ACK bit to full load operation Standby Current, Vbat = 3.6 V, Iout = 0 mA @ SCL = SDA = H (no port activity) Operating Current, @ Iout = 0 mA, Vbat = 3.6 V Maximum Inductor Peak Current Output Current Tolerance @ Vbat = 3.6 V, ILED = 10 mA, -25C < TA < 85C Boost Operating Frequency, -40C < TA < 85C Thermal Shut Down Protection Thermal Shut Down Protection Hysteresis Efficiency @ Vbat = 3.6 V, ESR < 150 mW, Coilcraft = LPQ3310-472, Cout = 1.0 mF (Note 5) ILED = 10 mA, Vf = 2.85 V ILED = 25 mA, Vf = 3.4 V 1.17 -15% 2.0 800 1 1.30 160 30 1.43 +15% 30 25 0.1 32 2.0 600 1.0 34 Min 2.7 2.3 2.4 75 Typ Max 5.5 2.5 Unit V V mV mA mA V V ms ISTBY Iop IPK ITOL FPWR TSD TSDH EPWR 1.0 mA mA mA % MHz C C % 75 80 5. Using low ESR inductor with low Eddy current losses is mandatory to get the high efficiency operation. http://onsemi.com 4 NCP5021 Table 4. ANALOG SECTION: (Typical values are referenced to Ta = +25C, Min & Max values are referenced -40C to +85C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted. Pin 7 6 Symbol IREF IPK kref kpk 7 6 9 VREF VREFK VFB MDCY 9 ILKGM FLF 4 4 4 VVSD RVSD ISDUSD GAMB0.25 GAMB0.50 GAMB01 GAMB02 GAMB04 5 Viph Rating Reference Current @ Vref = 1144 mV (Note 6) Reference Current @ Vref = 1144 mV (Note 6) Reference Current to ILED peak current ratio Reference Current to Inductor peak current ratio Reference Voltage (Note 6) Reference Voltage (Note 6) Feedback Voltage (Note 7) Boost Operating Maximum Duty Cycle Current Mirror Leakage Current Low Frequency Clock derived from the internal 1.3 MHz clock Photo Sense Bias Supply @ Ibias = 1 mA Photo Sense Bias Supply internal impedance Photo Sense Leakage Current Photo Sense Internal Gain 1/4 Photo Sense Internal Gain 1/2 Photo Sense Internal Gain 1 Photo Sense Internal Gain 2 Photo Sense Internal Gain 4 Photo Sense Input Voltage (Note 9) 0.25 0.5 1 2 4 1.5 V 0.6 2.5 30 100 92 -3% -10% Min 1.0 1.0 250 9700 1144 1144 425 94 200 20 Vbat +3% +10% mV mV mV % nA Hz V W nA Typ Max 100 100 Unit mA mA 6. The external circuit must not force the IREF or IPK pin voltage either higher or lower than the 1144 mV specified. The reference voltage applies to both IREF and IPK pins. 7. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended. 8. This parameter guarantees the function for production test purposes. 9. The ambient sense linearity is guaranteed when the voltage at the output of the internal amplifier is limited to 1.5 V. This voltage is equal to the input voltage times the programmed gain. Beyond this value, the operational amplifier is in the saturation region and the linearity is no longer guaranteed. Table 5. DIGITAL PARAMETERS SECTION (Typical values are referenced to Ta = +25C, Min & Max values are referenced -40C to +85C ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted. (Note 10) Symbol FSCK VIH VIL CIN VIH VIL Rating InputI2C clock frequency Positive going Input High Voltage Threshold, SCL, SDA signals Negative going Input High Voltage Threshold, SCL, SDA signals SDA Input Capacitance I2C address extension I2C address extension Vbat * 0.7 0 1.6 0 10 Min Typ Max 400 VBAT 0.4 15 Vbat + 0.3 V 0.3 Unit kHz V V pF V V 10. Digital inputs undershoot < -0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT http://onsemi.com 5 NCP5021 ESD Protection Circuit Depending upon the function of the pin, different circuitry is applied. The basic structure are illustrated in Figure 2. +Vcc D1 FET_P I/O Pin D2 FET_N Standard Low Voltage Structure GND High Voltage Structure DRIVER FET_N GND D1 Vz45V Vsw pin GND Figure 2. Typical ESD Protection Structures Although the structures are capable to handle the ESD stresses (as defined by the JEDEC specifications), no current or voltage, either DC or AC, beyond the maximum ratings specifications shall be applied to any pin. DC/DC Operation Vbat 2 Vbat L1 4.7uH Current Sense H1 + - H 3 2 1 D3 D4 I1 Iref 3 M9 1 3 2 2 1 M10 M8 D2 1 DNSR0320MW2T1 D5 470nF C1 The boost converter is based on a PWM structure to generate the output voltage necessary to drive the series arranged LED. The system includes an open load detection to avoid over voltage situation when the LED are disconnected from the Vout pin. A built-in circuit prevent high inrush current when the system is powered. The ILED is regulated by means of a built-in current mirror controlled by the digital content of the ILEDREG register. With a typical 1.3 Mhz operation frequency, the converter can run at full power with a tiny 4.7 mH inductor. However, cares must be observed, at ESR level, to optimize the total DC/DC conversion efficiency. In particular, the ferrite material shall have limited eddy current losses at high frequency. Depending upon the type of material, the eddy losses in the inductor can range from a low 40 mW to a high 250 mW under the same bias and load conditions. Table 6. RECOMMENDED INDUCTOR MANUFACTURERS Manufacturers TDK COILCRAFT MURATA LPQ3310-472 Part Number CONTROLLER D6 FEEDBACK Vbat Figure 3. Basic Boost Structure http://onsemi.com 6 NCP5021 Figure 4. Typical Switching Operation Although the total ohmic resistance plays an important role in the losses developed in the converter, the switching losses are key when the operating frequency is beyond a few kilohertz range. To minimize such losses, the internal power NMOS is designed to minimize the dI/dt, thus minimizing the I*V crossing time. As a consequence, the slope of the positive going voltage -VLX- present at the Lx pin is very fast as well and an overshoot is created since the Schottky rectifier has an intrinsic turn-on time: the voltage keeps going until the diode turns-on, clamping the VLX voltage at the output value. Such a mechanism is depicted in Figure 5. The proposed Schottky, depicted in the schematic Figure NO TAG, is a good alternative to minimize such an overshoot. On the other hand, the same overshoot is propagated to the Vout voltage when the system operates under open load condition. As a consequence, it is strongly recommended to implement a simple filter, built with a small footprint resistor, to makes sure that no any uncontrolled operation of the high sensitive pin Vos will happen under the worst case conditions: see Figure 1, resistor R5. Figure 5. Typical Turn On Time of the Schottky Rectifier http://onsemi.com 7 NCP5021 I2C Protocol The standard I2C protocol is used to transfer the data from the MCU to the NCP5021. Leaving aside the Acknowledge bit, the NCP5021 chip does not return data back to the MCU. The physical address of the NCP5021 can be selected as 0111 001X or 0111 010X (the X being the Read / Write identifier as defined by the I2C specification) depending upon the digital status present at the I2CADR pin: - I2CADR = Low address = %0111 0010 = $72 - I2CADR = High address = %0111 0100 = $74 First byte: Second byte: Third byte: I2C address, write register selection DATA In order to avoid any risk during the operation, the digital levels are intended to be hardwired either to GND or to Vbat prior to power up the system. The first byte of the I2C frame shall be selected address ($72 or $74) when a Write is send to the chip. To set up a new output current value, a full frame shall be send by the MCU. The frame contains three consecutive bytes and shall fulfill the I2C specifications (see Figure 6): $72 (assuming I2CADR = Low) %0000 0000 = internal register address %0000 0000 = function / output current value An infinite number of register selection / data pair can be send on the I2C port once the physical address has been decoded (see Figure 7). The transmission ends when the STOP signal is send by the SCL/SDA digital code. SCL SDA I2C Address Start Conditions SCL SDA I2C Address Register Selection DATA N sequences Register Selection DATA B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK Register Selection DATA Stop conditions Figure 6. Single Frame I2C Sequence Figure 7. Multi Frames I2C Sequence http://onsemi.com 8 NCP5021 Registers Setup Selection The register selection follows the I2C address of a new frame and must be followed by the DATA register. The content of the register selection byte is not stored into the chip and a new one shall be send for every DATA update. The low nibble contains the selected register number as depicted in Table 7. The high nibble is reserved for future use. Table 7. REGISTER SELECTION CODE $ 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The last code $0F is reserved for ON Semiconductor to control the manufacturing test and access to this register is not permitted outside the ON Semiconductor final test facilities. Shut Down the chip Select I-LED current setup and immediate LED update Set ILED target and Gradual Dimming UPWARD Set ILED target and Gradual Dimming DOWNWD Set timing and start the gradual dimming Reserved for future use Reserved for future use Reserved for future use Set up Photo sense input stage gain Set up Photo Sense I-LED minimum value Set up Photo Sense up/down timing Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for manufacturing test: do not access Table 8. REGISTERS IDENTIFICATION DEC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Shut Down the chip Select I-LED current setup and immediate LED update Select I-LED target Gradual Dimming command UP Select I-LED target Gradual Dimming command DOWN Set Timing & Start gradual Dimming Sequence Reserved for future use Reserved for future use Reserved for future use Set up Photo sense input stage gain Set up Photo Sense I-LED minimum value Set up Photo Sense timing Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for manufacturing test: do not access FTEST[7..0] PHGAIN[4..0] PHMIN[3..0] PHCLK[5..0] $08 $09 $0A $0B $0C $0D $0E $0F Register Functions Register Identification SDN ILEDREG[4..0] GDIM[4..0] GDIM[4..0] TDIM[4..0] Command $00 $01 $02 $03 $04 http://onsemi.com 9 NCP5021 ILED Peak Current The ILED peak current depends upon the reference current (IREF pin) and the digital contain of the ILEDREG register. The I2C port is used to setup the ILED peak current stored into the ILEDREG register. The load current is derived from the 1144 mV reference voltage provided by the internal Band Gap associated to the external resistor connected across IREF pin and Ground (see Figure 8). The maximum ILED current is given by the internal current mirror ratio (multiplier - k -) equal to 250. In other word, to get a 25 mA maximum, with a full $1F command, the reference current shall be 25 mA/250 = 100 mA. This current is used to calculate the resistor connected between the IREF pin and GND: RREF = 1.144 / 100e-6 = 11.44 kW. In any case, no voltage shall be forced at IREF pin, either downward or upward. The tolerance of the external resistor must be 1% or better, with a 100 ppm thermal coefficient, to get the expected overall tolerance. VBandGap 600mV LED Return Pin 2 & 3 GND R1 IREF Pin 4 GND Figure 8. Basic Reference Current Source NOTE: The IREF pin must never be biased by an external voltage higher than 1.44 V. The ILED current is given by Table 9 as a percentage of the maximum programmed ILED value (100% will give 25 mA when Iref = 100 mA). Table 9. OUTPUT CURRENT PROGRAMMED VALUE (Iout % = F(Step)) $Step 00 01 02 03 04 05 06 07 Iout % 0.00 0.10 0.13 0.16 0.20 0.25 0.32 0.40 Step 08 09 0A 0B 0C 0D 0E 0F Iout % 0.50 0.63 0.79 1.00 1.26 1.58 2.00 2.51 $Step 10 11 12 13 14 15 16 17 Iout % 3.16 3.98 5.01 6.31 7.94 10.00 12.59 15.85 $Step 18 19 1A 1B 1C 1D 1E 1F Iout % 19.95 25.12 31.62 39.81 50.12 63.10 79.43 100.00 http://onsemi.com 10 NCP5021 100 HORUS : Iout %= F(Step) Iout % 10 Iout (%) 1 0.1 -0.1 10 STEP 20.1 30.2 Figure 9. Typical ILED Programming Curve ILEDREG[0..7] I-LED PEAK CURRENT B7 step RESET 0 0 B6 0 0 B5 0 0 B4 ILED16 0 B3 ILED8 0 B2 ILED4 0 B1 ILED2 0 B0 ILED1 0 Bits [B7:B5] : Reserved for future use Bits [B4:B0] : ILED peak current setup Inductor Peak Current The peak current flowing into the inductor during normal application is set up by the external resistor RPCA connected between the IPK pin and ground. The maximum IPK current is given by the internal current mirror ratio (multiplier - kk -) typically equal to 9700. In other word, to get a 750 mA maximum peak current in the inductor, the reference current shall be 750 mA/9700 = 79 mA. This current is used to calculate the resistor connected between the IPK pin and GND: RREF = 1.144 / 79e-6 = 14.4 kW. The concept depicted in the ILED peak current paragraph applies as well and cares must be observed to avoid any voltage source connection to the IPK pin. Gradual Dimming The purpose of that function is to gradually Increase or Decrease the brightness of the backlight / keyboard LED upon command from the external MCU. The function is activated and controlled by means of the I2C protocol. The period (either upward or downward) is equal to the time defined for each step, multiplied by the number of steps. The number of step is derived from the value associated with the target current. To operate such a function, the MCU will provide three information: 1. The target current level (either upward or downward) 2. The time per step 3. The Upward or Downward mode of operation When a new gradual dimming sequence is requested, the output current increases, according to the logarithmic curve, from the existing start value to the end value. The end current value is defined by the contain of the Upward or Downward register, the width of each step is defined by the third register, the number of step being in the 1 to 32 range ($00 to $1F). In the event of software error, the system checks that neither the maximum output current (25 mA), nor the zero level are forced out of their respective bounds. Similarly, software errors shall not force NCP5021 into an uncontrolled mode of operation. The dimming is built with 32 steps and the time delay encoded into the third byte of the I2C transaction. When the gradual dimming is not requested (register selection = $01), the output current is straightforwardly set up to the level defined by the contain of the related register upon acknowledge of the output current byte. The gradual dimming sequence must be set up before a new output current data byte is send to NCP5021. At this point, the brightness sequence takes place when the new data byte is acknowledged by the internal I2C decoder. Since the six registers are loaded on independent byte flow associated to the I2C address, any parameter of the NCP5021 chip can be updated ahead of the next function. http://onsemi.com 11 NCP5021 Table 10. GDIMR[7..0] GRADUAL DIMMING TARGET B7 ms RESET 0 0 B6 0 0 B5 0 0 B4 ILED5 0 B3 ILED4 0 B2 ILED3 0 B1 ILED2 0 B0 ILED1 0 Bits [B7:B5] : Reserved for future use Bits [B4:B0] : ILED peak current setup or Gradual Dimming Timing The number of step for a given sequence, depends upon the start and end output current range: since the IPEAK value is encoded in the ILEDREG [4:0] binary scale, a maximum of 31 steps is achievable during a gradual dimming operation. First byte: Second byte: Third byte: First byte: Second byte: Third byte: = 0111 0000 = 0000 0010 = 0000 1111 = 0111 0000 = 0000 0100 = 0000 0010 To select the direction of the gradual dimming (either Upward or Downward), one shall send the appropriate register before to activate the sequence as depicted in the example here below: I2C address (assuming I2CADR = Low) select an ILED target UPWARD sequence set I-LED = 2.51% of the maximum range I2C address (assuming I2CADR = Low) set Timing and start the sequence set Timing per step = 20 ms / step Table 11. TDIM[7.0] GRADUAL DIMMING TIME PER STEP B7 ms RESET 0 0 B6 0 0 B5 0 0 B4 160 0 B3 80 0 B2 40 0 B1 20 0 B0 10 0 Bits [B7:B5] : Reserved for future use Bits [B4:B0] : Gradual Dimming Timing Figure 10. Typical Gradual Dimming UPWARD http://onsemi.com 12 NCP5021 Figure 11. Typical Gradual Dimming DOWNWARD Backlight Dimming The built-in I2C interface provides a simple way to accurately control the output peak current flowing in the LED. The internal register ILEDREG[7:0] is set up by the content of the SDA byte send by the external MCU. For Table 12. ILEDREG[0..7] B7 step RESET 0 0 B6 0 0 B5 0 0 B4 typical application, the 100 mA reference current forced by the external resistor yields a 25 mA maximum in the output LED. The waveforms given on illustrate a normal programming sequence. B3 ILED8 0 B2 ILED4 0 B1 ILED2 0 B0 ILED1 0 ILED16 0 [B7:B6] = Reserved for future use [B4..B0] = Output LED mA/step current. The content of these bits is latched to the current reference on the 8th SCL clock pulse. Ambient Light Control The ambient light can be monitored, by an extra photo diode, to automatically adjust the I-LED peak current as a function of the ambient light. A dedicated I2C command is used to activated or de-activated this function. On the other hand, the end user shall set up the maximum I-LED current by means of an I2C command. The photo sense is automatically de-activated when an I2C command is send through the port, and resume to the pre-programmed status when the I2C command is completed. The concept is based on analog monitoring of the I-LED current and the photo sense feedback, associated to a Up/Down counter to properly setup the contrast at display level. The photo sense action is bounded by two limits: 1. upper I-LED as defined by the en user : the photo sense cannot increase the I-LED above such a limit 2. lower I-LED as defined by the en user : the photo sense cannot reduce the back light current to zero. When the photo sense activates the counter (in either direction), a selectable low frequency clock drive the counter, yielding a smooth and slow brightness variation. The 100 Hz noise, coming from the standard fluorescent tubes, is filter out by means of an external network built between the photo sensor and the AMBS pin. Generally speaking, such a filter is built with a RC network designed to cope with the electrical performances of the selected photo sense. As a consequence, the AMBS pin is biased by a low level voltage signal and processed accordingly the ambient light control structure: see Figure 15. http://onsemi.com 13 NCP5021 VSB 4 U3 SFH5711 Log +VBat VSB GAIN 4 2 R1 22k GND R/4 GND R/2 R 2R 4R Digital Gain Adjust R2 220k 1 AMBS 5 C1 2.2uF R R/2 GND U1 R ANALOG MONITORING I2C Figure 12. Basic Photo Sense Input Circuit Since several type of photo sensor can be used in the final application, provisions have been taken into account to dynamically adjust the gain of the photo current. Such capability is carried out by the internal register loaded through the I2C port. Table 13. PHGAIN[0..7] B7 VSD RESET 0 B6 0 0 B5 0 0 B4 PHG5 0 B3 PHG4 0 B2 PHG3 0 B1 PHG2 0 B0 PHG1 0 Bit [B7] : Photo sense VSD bias control Bit [B7] : B7 = 0 VSD disconnected, photo sense function de-activated Bit [B7] : B7 = 1 VSD connected, photo sense function activated Bits [B6:B5] : RFU Bits [B4:B0] : Photo sensor gain adjust When the photo sense returns a lower ambient light level in comparison to the maximum level set up by the user, the I-LED decreases with a timing defined by an I2C command. Such a timing is derived from the Low Frequency clock and selected by the PHTIM register (see Figure 13). Table 14. PHCLK[0..7] B7 PHTT RESET 0 B6 0 0 B5 PHT6 0 B4 PHT5 0 B3 PHT4 0 B2 PHT3 0 B1 PHT2 0 B0 PHT1 0 Bits [B7] : RFU Bits [B6] : RFU Bits [B5:B0] : PHT1 = Photo sense clock = 25 Hz PHT2 = Photo sense clock = 12 Hz PHT3 = Photo sense clock = 6 Hz PHT4 = Photo sense clock = 3 Hz PHT5 = Photo sense clock = 1.5 Hz PHT6 = Photo sense clock = 0.7 MHz PHTT = Photo sense clock = 1.7 MHz NOTE: T = 40 ms/step T = 80 ms/step T =160 ms/step T = 320 ms/step T = 640 ms/step T = 1280 ms/step T = 560 ns/step reserved for test purpose The bits cannot be combined to generate a different timing. http://onsemi.com 14 NCP5021 The PHTT bit is reserved for ON Semiconductor test purposes and shall not be asserted High by the end user outside the ON Semiconductor final test facilities. When the PHTT is asserted High, the I-LED jumps instantaneously from the previous level to the end value. Phot Sense AMBS I-LED maximum I-LED minimum PHTIM 16ms to 7500ms PHTIM 16ms to 7500ms Figure 13. Basic Photo Sense Timing The rise and fall time of the I-LED current are programmable (according to the PHTIM register contain) and identical. The timing is defined by the PHTIM[B4:B0] bits multiplied by the number of steps necessary to reduce / increase the I-LED form one value to the next limit. Table 15. PHMIM[0..7] B7 0 RESET 0 B6 0 0 B5 0 0 B4 0 0 On the other hand, the I-LED cannot be reduce to zero during the Photo sense operation: the contain of the PHMIN[B2:B0] register limits the low end current when the photo sensor is in a dark environment. B3 PHM4 0 B2 PHM3 0 B1 PHM2 0 B0 PHM1 0 Bits [B7:B4] : RFU Bits [B3:B0] : set up the I-LED minimum value, according to the logarithmic table. ILED Max (25 mA, programmable) Ambient Light Gradual Dimming: Photo sense de-activated I-setup ILED Min (Programmable) Photo Sense The photo sense register is loaded with the I2C content Ambient Light < I2C ILED: the Photo sense controls the ILED The Photo Sense cannot force the ILED below the pre-programmed minimum level The Photo Sense controls ILED within the Imin and I-setup limits When a Downward Gradual Dimming is engaged, the ILED is reduced from the level defined by the Photo sense to the lower value defined by the gradual dimming register containt. Figure 14. Basic Gradual Dimming and Photo Sense Operation Strategy http://onsemi.com 15 NCP5021 Figure 15. Basic Ambient Photo Sense Regulation (PSPICE Simulation) http://onsemi.com 16 NCP5021 PACKAGE DIMENSIONS UQFN16 3x3, 0.5P CASE 523AF-01 ISSUE A D A B L 0.10 C 2X 0.10 C TOP VIEW DETAIL B DETAIL B OPTIONAL CONSTRUCTION 4X SCALE A 0.05 C 17X A3 0.05 C NOTE 4 A1 SIDE VIEW D2 5 C SEATING PLANE DETAIL A K 9 e/2 e E2 1 13 16X 16X L b 0.10 C A B 0.05 C NOTE 3 1 16X BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative http://onsemi.com 17 II II 2X CCC CCC CCC PIN ONE REFERENCE E DETAIL A OPTIONAL CONSTRUCTION 2X SCALE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.20 0.30 3.00 BSC 1.60 1.80 3.00 BSC 1.60 1.80 0.50 BSC 0.20 --- 0.30 0.50 SOLDERING FOOTPRINT* 0.50 PITCH 16X 0.60 1.55 3.30 2X 2X 0.29 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. NCP5021/D |
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